frequency divider
英 [ˈfriːkwənsi dɪˈvaɪdə(r)]
美 [ˈfriːkwənsi dɪˈvaɪdər]
分频器（管）
双语例句
- N is the desired noninteger frequency divider.
n为所要求的非整数分频值。 - A programmable multi-modulus frequency divider is designed and implemented in a0.
多模基带处理器是一种兼容多标准的通信平台。 - Unwanted and meaningless information in input, storage and output. It was used as a frequency divider and no numbers are decoded from it.
在输入、存储及输出过程中无用且无意义的信息。它被用作无解码输出的分频器。 - Design and precision analysis of dual-modules frequency divider with regulable duty ratio
一种可调占空比型双模分频器设计及精度分析 - The comparison of digital frequency divider and traditional analog frequency divider shows that the former is more superadded.
比较了数字分频器与传统模拟分频器，说明数字分频器更具优点。 - Design and Realization of Frequency Divider in Servo Drivers Based on FPGA
基于FPGA的伺服驱动器分周比设计与实现 - Experiment of fourfold frequency divider proved the feasibility and validity of the method.
四倍分频器电路演化实验结果验证了该方法的可行性与有效性。 - Design of Odd and Decimal Frequency Divider Circuit Based on LUT
基于查找表LUT结构的奇数与小数分频电路设计 - A novel edge-triggered D-flip-flop based on a resonant tunneling diode ( RTD) is proposed and used to construct a binary frequency divider.
提出了一种基于共振隧穿二极管的新型边沿触发D触发器并将之用于构成二进制分频器。 - The analysis of spike pulse noise rejection, frequency divider and dead time in oscillator and control circuit;
振荡器和控制电路中尖峰脉冲噪声抑制、两分频电路及死区时间设定； - A millimeter wave phase-locked source was designed by the principle of miniaturization and low phase noise. Some high-performance components, such as phase-locked loop, frequency divider, integrated VCO, etc.
依据小型化、低相位噪声原则设计了毫米波锁相源.在实现方案中，选用了高性能的锁相环、分频器和集成VCO等器件； - Verilog HDL design of frequency divider in RTC module is studied here.
文中研究在RTC模块中分频器设计的Veriloghdl实现。 - The high-speed electric signals at internal points in the high-speed GaAs digital integrated circuit-dynamic frequency divider were measured.
利用该系统在片检测了GaAs高速数字集成电路动态分频器内部的高速电信号。 - A very low phase noise 2~ N frequency divider is presented.
介绍了一种低相位噪声2N分频器的设计。 - This paper discusses the design of phase-locking frequency synthesis oscillator with low phase noise, and analyses and discusses the main causes for its phase noise such as loop filter, frequency divider, phase discriminator and voltage control oscillator ( VCO).
主要讨论了低相位噪声微波锁相频率合成器的设计，并对影响其相位噪声的主要因素如环路滤波器、分频器、鉴相器及压控振荡器（VCO）分别作了分析和讨论； - This paper gives out a design of the equal duty ratio arbitrary integer frequency divider based on FPGA.
给出了一种基于FPGA的等占空比任意整数分频电路的设计方法。 - This system is composed of a frequency divider, waveform generator, vector signal source and wideband amplifier.
该系统完全基于仪器设备（分频器、波形发生器、宽带放大器和具有I/Q调制功能的矢量信号发生器），无任何专门设计的电子线路。高频剔除的原理是激励粒子横向振荡而丢失。 - This frequency divider is applicable for SDH STM 1/ 4 optic fiber communication system.
本文提出的电路适用于SDHSTM-1/4的光纤通信系统。 - A fundamental principle of the dynamic frequency divider is introduced.
本文介绍了动态分频器的基本原理； - In the end, the phase noise performance of subharmonic sampling phase-locked loop and digital PLL using frequency divider are analyzed and compared. The result shows that the former has more superior phase noise performance if both of the PLLs use the same reference and VCO.
最后分析和比较了分谐波采样式锁相环和分频式锁相环的相位噪声性能，得出了在相同的参考源和压控振荡器条件下，前者的相位噪声性能更优的结论。 - The logic and circuit design of a very high speed ECL programmable frequency divider is described.
介绍一种ECL高速程控分频器的逻辑设计、电路设计及研制结果。 - The frequency divider implemented in a 0.18 μ m CMOS process is used in WCDMA system.
分频器电路采用0.18μMCMOS工艺设计，用于WCDMA通讯系统中。 - Quasi-sample circuit composed of frequency divider avoids the glitch of the output signal affecting subsequent circuits ( like comparators in ADC).
采用由分频器组成的准采样电路，避免了保持输出信号的抖动对后级电路（如ADC的比较器）的影响。 - Latch is the basic unit of frequency divider.
作为分频器的基本单元，锁存器的工作速度直接影响了分频器的性能。 - The circuit design, fabrication, and performance of high-speed AlGaAs/ GaAs HBT D-type flip flop and static frequency divider integrated circuits are described.
叙述了高速AlGaAs/GaAsHBTD-触发器和静态分频器的设计、制造和性能。 - In addition, fractional frequency divider has greatly reduced error in baud rate.
另外，采用小数分频等技术极大地降低了串口的波特率误差。 - The digital part includes closed loop oscillator, frequency divider, combinational logic circuit, non-overlapping clock generation circuit.
数字部分包含环形振荡器、分频器、组合逻辑门、非交叠时钟产生电路。 - We can input the setting value and control signal to get the results of frequency divider and circuit designing by a series of signal processing in order to start a scaling-down process.
要想实现一次分频工作过程，只要通过键盘输入设定值和控制信号，就可以通过一系列信号处理过程，最终得到分频的结果和设计电路。 - The entire charge pump PLL contained five parts which they are PFD, voltage control oscillator, charge pump, loop filter and frequency divider.
整个电荷泵锁相环包括鉴频鉴相器、电荷泵电路、环路滤波器、压控振荡器和分频器五部分。 - The divider phase noise and power consumption analysis, frequency divider phase noise and power consumption are mainly from the first RF fixed two dividers, determines the module design is to reduce the power consumption of the key.
通过对分频器相位噪声和功耗的分析，分频器相位噪声和功耗主要来自于第一级射频固定二分频器，确定该模块设计是降低功耗的关键。